1. Technical Field
The present invention relates to the improvement of signal processing. More specifically, the present invention pertains to signal processing circuits that operate in synchronization with a clock signal and signal processing methods for use in LSI (large-scale integrated) circuits such as microprocessors and signal processors. This invention is further directed to the reduction of electric power consumption in circuits such as switch circuits and latch circuits which operate in response to clock signals.
2. Background Art
In conventional signal processing circuits, particularly, in a very fast digital signal processing circuit of a semiconductor integrated circuit, a pipeline is formed by dividing a logic circuit or an arithmetic unit into an adequate number of stages and by placing a switch circuit and a latch circuit between each stage, to improve the throughput of signal processing.
With reference to FIG. 9, one stage of such a pipeline structure is described. CLK indicates a clock signal. 100 is an inverter circuit which receives and inverts the clock signal CLK. 101 is another inverter circuit which receives and inverts the output Q of the inverter circuit 100.
SW1 is a first switch circuit. The first switch SW1 receives the output Q of the inverter circuit 101 and the output XQ of the inverter 101. On the rising edge of the clock signal CLK, the first switch SW1 turns on, as shown in FIG. 10. 102 is a latch circuit, comprised of a switch circuit 102a and two inverter circuits 102b and 102c, receives DATA A through the first switch SW1 when the first switch circuit SW1 turns on. This DATA A is latched by the latch circuit 102 when the first switch SW1 subsequently turns off. SW2 is a second switch circuit. The second switch circuit SW2 receives the output Q of the inverter circuit 100 and the output XQ of the inverter circuit 101. The second switch circuit SW2 turns on, on the falling edge of the clock signal CLK (FIG. 10) and outputs, to a subsequent stage, LATCH DATA B of the latch circuit 102 as DATA C.
This conventional signal processing circuit, however, has the following drawbacks. When no data changes occur between clock signal cycles, the transfer of data between pipelines is not essentially required. However, in the switch circuits SW1, SW2 and 102a and the inverter circuits 100 and 101, the gate electrode capacitance of transistors forming these circuits is charged or discharged every time the clock signal CLK rises or falls. The gate electrode capacitance is charged or discharged even when LATCH DATA XB of the latch circuit 102 is identical with the next INPUT DATA A, which increases the power consumption by a proportional amount to such charge/discharge. In other words, the switch circuits SW1, SW2 and 102a and the inverter circuits 100 and 101 operate, regardless of the contents of transfer data, with their gate electrode capacitance repeatedly charged or discharged in synchronization with the system clock signal CLK. As a result of such charge/discharge, extra electric power is wasted. Especially, in the idling state, that is, when the clock signal is still supplied although the arithmetic unit is in the non-operation mode, further extra electric power is wasted.